ACADEMIC PROJECT · VERILOG · NEXYS A7

FPGA Digital Combination Lock

A five-switch combination lock with timed password verification, LED and seven-segment status indicators, automatic relocking, and an external audible alert.

VerilogXilinx VivadoNexys A7Digital Logic

Actual annotated Nexys A7 FPGA board with the switches, seven-segment display, LEDs, reset button and buzzer output. — My actual Nexys A7 board, annotated to show the hardware used in the project.

01 / OVERVIEW

FPGA-Based Access Control

I developed a digital combination lock using Verilog HDL and a Digilent Nexys A7 FPGA. Five physical switches provide password input. The design evaluates the combination after a programmed stability interval and uses the seven-segment display, LEDs, and an external buzzer for status feedback.

02 / OPERATION

Lock and Unlock Behavior

The intended timing includes a one-second stable-input interval, a five-second unlocked period, and a two-second incorrect-entry buzzer alert. The rightmost seven-segment digit shows a complete L when locked and U when unlocked; the green and red LEDs provide additional feedback.

03 / DEVELOPMENT

Hardware and Logic Gallery

Annotated photograph of the Nexys A7 FPGA board — Annotated Nexys A7 hardware and input/output connections.

Password comparison logic diagram — Five-bit password comparison logic diagram.

FPGA project development photograph three — Early test showing the multiple-digit display issue before debugging.

04 / DEBUGGING

Technical Challenges

Multiple digits illuminated

I corrected the active-low digit-enable setting so that only the rightmost digit displayed L or U.

Briefly flashing U

I debugged the Verilog so U remained visible during the unlocked period.

Continuous buzzer activation

I corrected an issue where the external buzzer sounded regardless of whether the password was correct or incorrect.

Reverse-current issue

I modified the external buzzer circuit and added a diode to address unwanted reverse current.

05 / EXTENSION

Three-Attempt Security Logic & Future Work

I developed a three-attempt controller and worked on integrating it into the main lock design. The updated integration has not been verified on the physical FPGA. Another future improvement is allowing users to change the password without modifying and reprogramming the Verilog.

06 / VIDEO

Development Demonstration

Early FPGA Test

SKILLS IN PRACTICE

Skills Applied

Here is how the tools and techniques from my Technical Skills section were applied to this project.

Verilog / Vivado

Programmed and debugged the Nexys A7 combination-lock logic, timed behavior and seven-segment display.

Circuit Design

Connected the external buzzer and added a diode to address unwanted reverse current.

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